The present invention relates to Plasma Display Panel (PDP) gate drivers, and more particularly to an automatic high voltage gate driver IC (HVIC) for PDP.
PDP HVICs include an internal logic functional block for a PDP sustain driver. FIG. 1 shows a conventional PDP sustain driver 10, which is a half-bridge driver with soft switching for a capacitive load. The PDP sustain driver 10 consists of four switches, including a rising switch 12, a falling switch 14, a sustain switch 16, and a ground switch 18. These switches may be n-channel type field effect transistors. The PDP sustain driver 10 further includes a capacitor 20, diodes 24 and 26, and an inductor 28. Capacitor 22 represents the Plasma Display Panel capacitance CP.
A conventional sustain driver 10 requires four input signals, the four input signals being connected to gates of each of the switches 12, 14, 16, and 18, each signal driving a unique switch. FIG. 2 shows a conventional sustain driver 30 that uses four input signals. It includes four switches 12, 14, 16, and 18; capacitor 20; diodes 24 and 26 and an inductor 28. Capacitor 22 (CP) is the panel capacitance. The driver 30 further includes a signal buffer 36 and two HVICs 32 and 34. The signal buffer 36 receives four signals, a signal ERR for the rising switch 12, a signal SUS for the sustain switch 16, a signal ERF for the falling switch 14, and the signal GRND for a ground switch 12. The HVIC 32 is connected to and controls the rising switch 12 and the sustain switch 16. The HVIC 34 is connected to and controls the falling switch 14 and the ground switch 18. Accordingly, each switch 12, 14, 16, and 18 is independently controlled. This, however, commands high cost and space for a four input signal printed circuit board (PCB) pattern, as well as multiple cables from a timing controller and the signal buffer 36.
The switch 16 has one end connected to a power supply terminal (VBUS). The switch 18 has one end connected to the ground terminal; the other ends of the switches 16 and 18 are interconnected at a node A. The node A is connected to a plurality of sustain electrodes represented in FIG. 1 as a panel capacitance CP 22 corresponding to the total capacitance between the plurality of sustain electrodes and the ground terminal.
The switch 12 and the diode 24 are series connected between the node B and the recovering capacitor Cr 20 that is also connected to the ground terminal. The diode 26 and switch 14 are similarly connected in series between the node B and the recovering capacitor Cr 20.
When the control signal to the switch 18 attains a low level, the switch 18 turns off, while when the control signal to the switch 12 attains a high level, the switch 12 turns on. At the time, the control signal to the switch 16 is at a low level, and the switch 16 is in an off state, while the control signal to the switch 14 is at a low level, and the switch 14 is in an off state. Therefore, the recovering capacitor Cr 20 is connected to the recovering coil 28 through the switch 12 and the diode 24, and LC resonance by the recovering coil 24 and the panel capacitance CP 22 causes the voltage at the node A to gradually rise. At the time, charges from the recovering capacitor Cr 20 are discharged to the panel capacitance CP 22 through the switch 12, the diode 24 and the recovering coil 28. The sustain switch 16 turns on after switch 12 to sustain the charge on the panel CP. Later, ERF switch 14 turns on to discharge the panel into Cr and GND switch 18 turns on even later to maintain the discharge. Then the cycle repeats to keep the current alternately flowing into the panel CP.